2.4.14

 arch

 i386

 kernel

diff -u --recursive --new-file v2.4.13/linux/arch/i386/kernel/setup.c linux/arch/i386/kernel/setup.c
--- v2.4.13/linux/arch/i386/kernel/setup.c   Tue Oct 23 22:48:49 2001
+++ linux/arch/i386/kernel/setup.c   Thu Oct 25 13:53:46 2001
@@ -229,8 +229,7 @@
 
 #define   SIO_PM_GP_EN   0x80
 
-static void
-visws_get_board_type_and_rev(void)
+static void __init visws_get_board_type_and_rev(void)
 {
    int raw;
 
@@ -402,7 +401,7 @@
    }
 }
 
-void __init add_memory_region(unsigned long long start,
+static void __init add_memory_region(unsigned long long start,
                                   unsigned long long size, int type)
 {
    int x = e820.nr_map;
@@ -667,7 +666,7 @@
  */
 #define LOWMEMSIZE()   (0x9f000)
 
-void __init setup_memory_region(void)
+static void __init setup_memory_region(void)
 {
    char *who = "BIOS-e820";
 
@@ -699,7 +698,7 @@
 } /* setup_memory_region */
 
 
-static inline void parse_mem_cmdline (char ** cmdline_p)
+static void __init parse_mem_cmdline (char ** cmdline_p)
 {
    char c = ' ', *to = command_line, *from = COMMAND_LINE;
    int len = 0;
@@ -1263,11 +1262,11 @@
 /*
  * Read Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  */
-static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
+static void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
 {
    unsigned char ccr2, ccr3;
    unsigned long flags;
-
+   
    /* we test for DEVID by checking whether CCR3 is writable */
    local_irq_save(flags);
    ccr3 = getCx86(CX86_CCR3);
@@ -1303,7 +1302,7 @@
  * Actually since bugs.h doesnt even reference this perhaps someone should
  * fix the documentation ???
  */
-unsigned char Cx86_dir0_msb __initdata = 0;
+static unsigned char Cx86_dir0_msb __initdata = 0;
 
 static char Cx86_model[][9] __initdata = {
    "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
@@ -1336,7 +1335,7 @@
 static void __init check_cx686_slop(struct cpuinfo_x86 *c)
 {
    unsigned long flags;
-
+   
    if (Cx86_dir0_msb == 3) {
       unsigned char ccr3, ccr5;
 
@@ -1503,6 +1502,248 @@
    return;
 }
 
+#ifdef CONFIG_X86_OOSTORE
+
+static u32 __init power2(u32 x)
+{
+   u32 s=1;
+   while(s<=x)
+      s<<=1;
+   return s>>=1;
+}
+
+/*
+ *   Set up an actual MCR
+ */
+ 
+static void __init winchip_mcr_insert(int reg, u32 base, u32 size, int key)
+{
+   u32 lo, hi;
+   
+   hi = base & ~0xFFF;
+   lo = ~(size-1);      /* Size is a power of 2 so this makes a mask */
+   lo &= ~0xFFF;      /* Remove the ctrl value bits */
+   lo |= key;      /* Attribute we wish to set */
+   wrmsr(reg+MSR_IDT_MCR0, lo, hi);
+   mtrr_centaur_report_mcr(reg, lo, hi);   /* Tell the mtrr driver */
+}
+
+/*
+ *   Figure what we can cover with MCR's
+ *
+ *   Shortcut: We know you can't put 4Gig of RAM on a winchip
+ */
+
+static u32 __init ramtop(void)      /* 16388 */
+{
+   int i;
+   u32 top = 0;
+   u32 clip = 0xFFFFFFFFUL;
+   
+   for (i = 0; i < e820.nr_map; i++) {
+      unsigned long start, end;
+
+      if (e820.map[i].addr > 0xFFFFFFFFUL)
+         continue;
+      /*
+       *   Don't MCR over reserved space. Ignore the ISA hole
+       *   we frob around that catastrophy already
+       */
+                
+      if (e820.map[i].type == E820_RESERVED)
+      {
+         if(e820.map[i].addr >= 0x100000UL && e820.map[i].addr < clip)
+            clip = e820.map[i].addr;
+         continue;
+      }
+      start = e820.map[i].addr;
+      end = e820.map[i].addr + e820.map[i].size;
+      if (start >= end)
+         continue;
+      if (end > top)
+         top = end;
+   }
+   /* Everything below 'top' should be RAM except for the ISA hole.
+      Because of the limited MCR's we want to map NV/ACPI into our
+      MCR range for gunk in RAM 
+      
+      Clip might cause us to MCR insufficient RAM but that is an
+      acceptable failure mode and should only bite obscure boxes with
+      a VESA hole at 15Mb
+      
+      The second case Clip sometimes kicks in is when the EBDA is marked
+      as reserved. Again we fail safe with reasonable results
+   */
+   
+   if(top>clip)
+      top=clip;
+      
+   return top;
+}
+
+/*
+ *   Compute a set of MCR's to give maximum coverage
+ */
+
+static int __init winchip_mcr_compute(int nr, int key)
+{
+   u32 mem = ramtop();
+   u32 root = power2(mem);
+   u32 base = root;
+   u32 top = root;
+   u32 floor = 0;
+   int ct = 0;
+   
+   while(ct<nr)
+   {
+      u32 fspace = 0;
+
+      /*
+       *   Find the largest block we will fill going upwards
+       */
+
+      u32 high = power2(mem-top);   
+
+      /*
+       *   Find the largest block we will fill going downwards
+       */
+
+      u32 low = base/2;
+
+      /*
+       *   Don't fill below 1Mb going downwards as there
+       *   is an ISA hole in the way.
+       */      
+       
+      if(base <= 1024*1024)
+         low = 0;
+         
+      /*
+       *   See how much space we could cover by filling below
+       *   the ISA hole
+       */
+       
+      if(floor == 0)
+         fspace = 512*1024;
+      else if(floor ==512*1024)
+         fspace = 128*1024;
+
+      /* And forget ROM space */
+      
+      /*
+       *   Now install the largest coverage we get
+       */
+       
+      if(fspace > high && fspace > low)
+      {
+         winchip_mcr_insert(ct, floor, fspace, key);
+         floor += fspace;
+      }
+      else if(high > low)
+      {
+         winchip_mcr_insert(ct, top, high, key);
+         top += high;
+      }
+      else if(low > 0)
+      {
+         base -= low;
+         winchip_mcr_insert(ct, base, low, key);
+      }
+      else break;
+      ct++;
+   }
+   /*
+    *   We loaded ct values. We now need to set the mask. The caller
+    *   must do this bit.
+    */
+    
+   return ct;
+}
+
+static void __init winchip_create_optimal_mcr(void)
+{
+   int i;
+   /*
+    *   Allocate up to 6 mcrs to mark as much of ram as possible
+    *   as write combining and weak write ordered.
+    *
+    *   To experiment with: Linux never uses stack operations for 
+    *   mmio spaces so we could globally enable stack operation wc
+    *
+    *   Load the registers with type 31 - full write combining, all
+    *   writes weakly ordered.
+    */
+   int used = winchip_mcr_compute(6, 31);
+
+   /*
+    *   Wipe unused MCRs
+    */
+    
+   for(i=used;i<8;i++)
+      wrmsr(MSR_IDT_MCR0+i, 0, 0);
+}
+
+static void __init winchip2_create_optimal_mcr(void)
+{
+   u32 lo, hi;
+   int i;
+
+   /*
+    *   Allocate up to 6 mcrs to mark as much of ram as possible
+    *   as write combining, weak store ordered.
+    *
+    *   Load the registers with type 25
+    *      8   -   weak write ordering
+    *      16   -   weak read ordering
+    *      1   -   write combining
+    */
+
+   int used = winchip_mcr_compute(6, 25);
+   
+   /*
+    *   Mark the registers we are using.
+    */
+    
+   rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+   for(i=0;i<used;i++)
+      lo|=1<<(9+i);
+   wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+   
+   /*
+    *   Wipe unused MCRs
+    */
+    
+   for(i=used;i<8;i++)
+      wrmsr(MSR_IDT_MCR0+i, 0, 0);
+}
+
+/*
+ *   Handle the MCR key on the Winchip 2.
+ */
+
+static void __init winchip2_unprotect_mcr(void)
+{
+   u32 lo, hi;
+   u32 key;
+   
+   rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+   lo&=~0x1C0;   /* blank bits 8-6 */
+   key = (lo>>17) & 7;
+   lo |= key<<6;   /* replace with unlock key */
+   wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+}
+
+static void __init winchip2_protect_mcr(void)
+{
+   u32 lo, hi;
+   
+   rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+   lo&=~0x1C0;   /* blank bits 8-6 */
+   wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+}
+   
+#endif
+
 static void __init init_centaur(struct cpuinfo_x86 *c)
 {
    enum {
@@ -1546,6 +1787,19 @@
             fcr_clr=DPDC;
             printk(KERN_NOTICE "Disabling bugged TSC.\n");
             clear_bit(X86_FEATURE_TSC, &c->x86_capability);
+#ifdef CONFIG_X86_OOSTORE
+            winchip_create_optimal_mcr();
+            /* Enable
+               write combining on non-stack, non-string
+               write combining on string, all types
+               weak write ordering 
+               
+               The C6 original lacks weak read order 
+               
+               Note 0x120 is write only on Winchip 1 */
+               
+            wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
+#endif            
             break;
          case 8:
             switch(c->x86_mask) {
@@ -1561,11 +1815,37 @@
             }
             fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
             fcr_clr=DPDC;
+#ifdef CONFIG_X86_OOSTORE
+            winchip2_unprotect_mcr();
+            winchip2_create_optimal_mcr();
+            rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+            /* Enable
+               write combining on non-stack, non-string
+               write combining on string, all types
+               weak write ordering 
+            */
+            lo|=31;            
+            wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+            winchip2_protect_mcr();
+#endif
             break;
          case 9:
             name="3";
             fcr_set=ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|E2MMX|EAMD3D;
             fcr_clr=DPDC;
+#ifdef CONFIG_X86_OOSTORE
+            winchip2_unprotect_mcr();
+            winchip2_create_optimal_mcr();
+            rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
+            /* Enable
+               write combining on non-stack, non-string
+               write combining on string, all types
+               weak write ordering 
+            */
+            lo|=31;            
+            wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
+            winchip2_protect_mcr();
+#endif
             break;
          case 10:
             name="4";